1. Field of Invention
The present invention relates to flash memory. More particularly, the present invention relates to a double-cell flash memory.
2. Description of Related Art
Non-volatile memory device, such as flash memory device, allows multiple times erase and program operation inside system. As a result, flash memory is suitable to many of advance hand-held digital equipments, including solid state disks, cellar phones, digital cameras, digital movie cameras, digital voice recorders, and PDA, that are demanding a low-cost, high-density, low-power-consumption, highly reliable file memory.
Conventionally, flash memory is characterized into two cell structures, in which one is double poly NAND type memory cell with Poly1 as a floating gate to store charges, and the other one is the single poly SONOS cell with SiN as storage node, wherein ONO represent the dielectric stack layer of oxide/nitride/oxide (O/N/O). FIGS. 1A–1B are cross-sectional views, schematically illustrating conventional stack gate NAND flash memory cell. In FIG. 1A, the conventional NAND flash includes numerous strings of series connected N-channel transistor. For one memory cell, it has the control gate 110 and the floating gate 112 stacked together. The control gates are respectively connected to the word lines WL0, WL1, . . . The selection transistor 106 and 108 are used to select a memory block. One source/drain (S/D) region of the selection transistor 106 is coupled to the corresponding bit line, while the S/D region of the selection transistor 108 is coupled to a voltage source Vss, which usually is a ground voltage. The memory cells are formed in a triple-well 104. Since the memory device a CMOS device with logic part, the triple-well 104 is also within a deep N-well 102, which is formed in the P-type substrate 100.
FIG. 1B is the cross-sectional structure along the word line direction with respect to FIG. 1A. The shallow trench isolation (STI) 116 structures are between cells. However, due to the necessary of alignment, the floating gate 112 has an overlap region 118 with the STI 116. The cause additional cell size by for example about 0.5 F. Here, F known by the ordinal skilled artisans represents the minimum size, such as critical dimension. The cell size for the conventional cell structure is 2.5 F×2.0 F.
The operation of NAND Flash utilizes channel FN programming and erase as shown in FIGS. 2A–2B. The threshold Vth is used to store the binary data. In FIG. 2A, the programming process is to bring a negative threshold value to the positive threshold value. The reverse direction is for the erase operation.
In FIG. 2B, according to the FN tunneling mechanism, when cell content is erased, the world line is applied a ground voltage while the TPW is applied with a positive voltage. As a result, electrons in the floating gate 120 are ejected to the substrate. When the programming operation is performed, the S/D region is applied a ground voltage while the world line is applied a positive voltage Vpp. As a result, the electrons are injected into the floating gate by tunneling effect. The operation is known by the skilled artisans, and is not further described.
For another design of SONOS type flash memory, the device operation of SONOS cell is adopted channel hot carrier programming and band-to-band (B—B) hot hole erase. Cell size of SONOS cell is around 4 F2. However the reliability of SONOS cell is very sensitivity to hot electron and hot hole stress during program and erase operation. FIG. 3A is a drawing, schematically illustrating the content distribution of the memory cells with O/N/O dielectric layer design. FIG. 3B is a drawing, schematically illustrating the operation mechanism for the memory cell with O/N/O dielectric layer design. In FIG. 3B, the gate dielectric layer is an ONO structure layer 122, in which the nitride layer serves as the storage layer.
For the programming operation, the one S/D region 126 is grounded, and the other S/D region is coupled to the bit line (BL) with a voltage VD, and the word line 124 is applied with a higher voltage. The hot electrons are tunneled into the nitride layer. When the erase operation is performed, the word line is applied with a negative voltage and bit line is applied with positive voltage. As a result, the B—B hot holes are injected into the nitride layer to annihilate with the trapped electrons. The operation mechanism is also known by the skilled artisans and is not further described.
Based on the programming and erase mechanism, the conventional stack gate NAND flash memory is designed as shown in FIG. 4A and FIG. 4B. FIG. 1A also shows the cross-sectional structure. In FIG. 4A, the gates SGD and SGS are two selection gates to select the memory block. One S/D regions 130 (dotted) beside the gate SGD is coupled to the bit line BL0, BL1, . . . BLn by the plug structures 132. One S/D region 130 beside the selection gate SGS is coupled to the source line 134 through the plug structures 136. There also are doped source region 130 in the substrate beside the world lines WL0, WL1, . . . WLn, which are also the gates of the transistors for the memory cells. The equivalent circuit structure is shown in FIG. 4B.
It should be noted that, the cell size is in the conventional cell array is 2 F×2.5 F=5 F2. The operation for the NAND string cell have eight NMOS Flash cell in series is for example shown in Table 1. The disadvantage of prior art for the stack gate NAND Flash at least that the cell size of prior invention is closely to 5 F2 that is limited by Floating Gate overlap Active. The SONOS Flash has the disadvantages at least that cell reliability is strongly affected by hot electron and hole stress during program and erase operation respectively.
TABLE 1Device operation of conventional NAND Flash memory cell.ProgramProgram(non-NODEERASE(selected)selected)ReadBLFGGNDVCC1 VSGDFGVCCVCCVCCWL0GND1/2VPP1/2VPPVCCWL1GND1/2VPP1/2VPPVCCWL2GND1/2VPP1/2VPPVCCWL3GND1/2VPP1/2VPPVCCWL4GND1/2VPP1/2VPPVCCWL5 (selectedGNDVPPVPPGNDWL)WL6GND1/2VPP1/2VPPVCCWL7GND1/2VPP1/2VPPVCCSGSFGGNDGNDVCCVSFGGNDGNDGNDP-WELLVPPGNDGNDGND